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19-1097; Rev 1; 9/96
KIT ATION EVALU E AILABL AV
Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
____________________________Features
o Chatter-Free Power Detector with Programmable Loss-of-Signal Outputs o 4mV Input Sensitivity (PECL Loss-of-Signal Interface Logic--MAX3766 o PECL Data Outputs o Single 5V Power Supply o 250ps Output Edge Speed o Low 15ps Pulse-Width Distortion o TTL Loss-of-Signal Interface Logic--MAX3761
_______________General Description
The MAX3761/MAX3762 limiting amplifiers, with 4mV sensitivity and PECL data outputs, are optimized for operation in low-cost, 622Mbps, LAN/ATM LAN fiber optics applications. An integrated power detector senses the input signal's amplitude. A received-signal-strength indicator (RSSI) gives an analog indication of the power level, while the complementary loss-of-signal (LOS) outputs indicate if the input power level exceeds the programmed threshold level. The LOS threshold can be adjusted to detect signal amplitudes between 3mVp-p and 100mVp-p, providing a 15dB LOS adjustment in fiber optic receivers. The LOS outputs have 3.5dB of hysteresis, which prevents chatter when input signal levels are small. The MAX3761's LOS outputs are compatible with TTL-logic levels. The MAX3762 has PECL LOS outputs. DISABLE and LOS can be used to implement a squelch function, which turns off the data outputs when the input signal is below the programmed threshold.
MAX3761/MAX3762
______________Ordering Information
PART MAX3761EEP MAX3761C/D MAX3762EEP MAX3762C/D TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 QSOP Dice* 20 QSOP Dice*
________________________Applications
622Mbps LAN/ATM LAN Receivers 155Mbps LAN/ATM LAN Receivers
*Dice are designed to operate from -40C to +85C, but are tested and guaranteed only at TA = +25C.
__________________Pin Configuration
_________Typical Operating Circuits
+5V VCC EN 10nF RSSI VCCO 100pF BYPASS SUPPLY CIN 5.6nF VIN+ CIN 5.6nF VINCZP CZN DISABLE LOS+ LOSOUTOUT+ 50 50 GNDO GND VTH SUB VCC - 2V CAZ 150pF
TOP VIEW
FILTER 1 RSSI 2 EN 3 VCC 4 VIN+ 5 VIN- 6 GND 7 SUB 8 CZP 9 CZN 10 20 DISABLE 19 LOS+ 18 LOS17 VCC
MAX3761 MAX3762
16 VCCO 15 OUT+ 14 OUT13 GNDO 12 VTH 11 INV
100pF +VCC
MAX3761
FILTER CFILTER INV
R1 100k
R2 22k
QSOP
MAX3762 at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3761/MAX3762
ABSOLUTE MAXIMUM RATINGS
VCC, VCCO............................................................-0.5V to +7.0V FILTER, RSSI, EN, VIN+, VIN-, CZP, CZN, DISABLE, LOS+, LOS-, INV, VTH...............-0.5V to (VCC + 0.5V) PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA Continuous Power Dissipation (TA = +85C) QSOP (derate 8.3mW/C above +70C) .......................667mW Operating Junction Temperature Range ...........-40C to +150C Processing Temperature (die) .........................................+400C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, DISABLE = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25C.) (Note 1) PARAMETER Power-Supply Current LOS Output TTL High LOS Output TTL Low LOS Output PECL High LOS Output PECL Low DISABLE Input Current DISABLE Input High DISABLE Input Low DISABLE Input PECL High DISABLE Input PECL Low PECL Data Output Voltage High (VOH) PECL Data Output Voltage Low (VOL) Disabled Differential Output Disabled Common-Mode Output MAX3761, IVCC MAX3762, IVCC MAX3761 MAX3761 (TA = +25C to +85C) (TA = -40C to +25C) -1150 -1830 2.65 0.8 -1160 -1470 -1150 -1830 -100 VCC - 0.7 -880 -1555 100 VCC -1.2 2.8 0.40 0.44 -880 -1555 100 CONDITIONS MIN TYP 25 30 MAX 37 46 UNITS mA V V mV mV A V V mV mV mV mV mV V
MAX3762 (Notes 2, 3) MAX3762 (Notes 2, 3) Logic high MAX3761 MAX3761 MAX3762 (Note 3) MAX3762 (Note 3) (Notes 2, 3) (Notes 2, 3) DISABLE = high DISABLE = high
Note 1: Dice are tested at TA = +25C. Note 2: Outputs terminated with 50 to VCC - 2V. Note 3: Voltage measurements are relative to VCC.
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
AC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, PECL outputs terminated with 50 to VCC - 2V, input 4mV to 2Vp-p, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25C.) (Note 5) PARAMETER Minimum LOS Assert Input Data-Output Edge Speed Data-Output Overshoot Pulse-Width Distortion Input Resistance LOS Hysteresis 20% to 80% (Note 6) (Notes 6, 7) Differential 223 - 1 PRBS, VTH = 1.8V 15 3900 3.5 CONDITIONS TA = -40C, 223 - 1 PRBS MIN TYP MAX 3.2 250 20 80 UNITS mV ps % ps dB
MAX3761/MAX3762
Note 5: AC parameters are guaranteed by design and characterization. Note 6: Input signal is a 1-0 pattern, 622Mbps. Note 7: PWD = [(width of wider pulse) - (width of narrower pulse)] / 2.
__________________________________________Typical Operating Characteristics
(MAX3761/MAX3762 EV kit, VCC = +5.0V, PECL outputs terminated with 50 to VCC - 2V, input is a 1-0 pattern, 622Mbps, TA = +25C, unless otherwise noted.)
MAX3762 SUPPLY CURRENT vs. TEMPERATURE
MAX3761/62-01
RSSI vs. INPUT AMPLITUDE AND DATA PATTERN
MAX3761/62-02
RSSI vs. INPUT POWER AND FREQUENCY
2.28 2.16 RSSI VOLTAGE (V) 2.04 1.92 1.80 1.68 1.56 1.44 1.32 1.20 500MHz
MAX3761/62-03
50 45 VCC = 5.5V 40 CURRENT (mA) 35 30 25 VCC = 5.0V 20 VCC = 4.5V 15 10 -40 -15 10 35 60
2.40 2.28 2.16 RSSI VOLTAGE (V) 2.04 1.92 1.80 1.68 1.56 1.44 1.32 1.20 1-0 PATTERN 223 - 1 PRBS PATTERN
2.40 10MHz
85
1
AMBIENT TEMPERATURE (C)
10 100 INPUT SIGNAL (mVp-p)
1000
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 INPUT POWER (dBm)
0
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3761/MAX3762
____________________________Typical Operating Characteristics (continued)
(MAX3761/MAX3762 EV kit, VCC = +5.0V, PECL outputs terminated with 50 to VCC - 2V, input is a 1-0 pattern, 622Mbps, TA = +25C, unless otherwise noted.)
RSSI vs. TEMPERATURE (622Mbps 223 - 1 PRBS)
MAX3761/62-04
LOS HYSTERESIS vs. TEMPERATURE (622Mbps 223 - 1 PRBS PATTERN)
MAX3761/62-05
LOS HYSTERESIS vs. TEMPERATURE (622Mbps 1-0 PATTERN)
ASSERT LEVEL SET TO APPROXIMATELY 2mVp-p
MAX3761/62-06
2.00 1.92 1.84 RSSI VOLTAGE (V) 1.76 1.68 1.60 1.52 1.44 1.36 1.28 1.20 -40 -20 0 20 40 60 VIN = 4mVp-p VIN = 16mVp-p VIN = 50mVp-p
4.00 3.75 HYSTERESIS (dB) 3.50 3.25 3.00 2.75 2.50 ASSERT LEVEL SET TO APPROXIMATELY 2mVp-p
8 7 HYSTERESIS (dB)
6
5 ASSERT LEVEL SET TO APPROXIMATELY 30mVp-p
ASSERT LEVEL SET TO APPROXIMATELY 30mVp-p -40 -20 0 20 40 60 80 100
4
3 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C)
80
AMBIENT TEMPERATURE (C)
DATA OUTPUT LEVELS (REFERENCE TO VCC)
MAX3761/62-07
DIFFERENTIAL OUTPUT vs. INPUT AMPLITUDE
PULSE-WIDTH DISTORTION (PS) 1280 DIFFERENTIAL OUTPUT (mV) 1160 1040 920 800 680 560 440 320 200 60 80 0.1m 1m 0.01 0.1 1 INPUT SIGNAL (Vp-p) 10 0 0.001
MAX3761/62-08
PULSE-WIDTH DISTORTION (622Mbps DATA RATE)
MAX3761/62-09
-0.8 VOH -1.0 VOLTAGE (V)
1400
50
40 -40C 30
-1.2
-1.4
20
-1.6
VOL
10 +85C 0.01 0.1 1 INPUT SIGNAL (Vp-p) 10
-1.8 -40 -20 0 20 40 AMBIENT TEMPERATURE (C)
LOS OPERATION WITH SQUELCHING
MAX3761/62-10
LOS OPERATION WITHOUT SQUELCHING
MAX3761/62-11
DATA OUTPUT SINGLE-ENDED (223 - 1 PRBS PATTERN)
INPUT = 4mVp-p TA = +85C
MAX3761/62-12
OUT+
OUT+
100mV/ div
LOS+
100mV/ div DATA IN
LOS+
50mV/ div DATA IN
5s/div
5s/div
500ps/div
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
____________________________Typical Operating Characteristics (continued)
(MAX3761/MAX3762 EV kit, VCC = +5.0V, PECL outputs terminated with 50 to VCC - 2V, input is a 1-0 pattern, 622Mbps, TA = +25C, unless otherwise noted.)
MAX3761/MAX3762
DATA OUTPUT SINGLE-ENDED (223-1 PRBS PATTERN)
MAX3761/62-13
RANDOM JITTER
MAX3761/62-14
RANDOM JITTER vs. POWER-SUPPLY NOISE FREQUENCY
DIFFERENTIAL OUTPUT RANDOM JITTER DATA INPUT AMPLITUDE = 16mVp-p INPUT AMPLITUDE POWER SUPPLY = 100mVp-p
MAX3761/62-15
10
INPUT = 2Vp-p TA = +85C
RANDOM JITTER (ps rms)
DIFFERENTIAL OUTPUT (OUT+ - OUT-) INPUT = 16mVp-p TA = +27C 1-0 PATTERN 622Mbps 200mV/ div
8
50mV/ div
6
4
2 500ps/div 200ps/div 103 104 106 105 FREQUENCY ON POWER SUPPLY (Hz)
______________________________________________________________Pin Description
PIN 1 2 3 4, 17 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 NAME FILTER RSSI EN VCC VIN+ VINGND SUB CZP CZN INV VTH GNDO OUTOUT+ VCCO LOSLOS+ DISABLE FUNCTION Sets the integration frequency of the power detector. Impedance at this node is approximately 500. Received-Signal-Strength Indicator. An analog DC voltage representing the input power. Connect to VCC. +5V Power Supply Positive Input Data Negative Input Data Supply Ground Substrate. Connect to ground. Sets input offset correction, low-frequency cutoff. Sets input offset correction, low-frequency cutoff. Negative Input to Op Amp. Used for programming the loss-of-signal threshold. Loss-of-Signal Threshold Voltage Ground Power Supply for Output Buffers Negative PECL Data Output Positive PECL Data Output +5V Power Supply for Output Buffers Negative Loss-of-Power Flag, TTL (MAX3761) or PECL (MAX3762) Positive Loss-of-Power Flag, TTL (MAX3761) or PECL (MAX3762) Disables the data outputs when high. TTL (MAX3761) or PECL (MAX3762).
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3761/MAX3762
CAZ VCC GND SUB CZP CZN EN VCCO DISABLE LIMITER VIN+/VINLIMITER LIMITER LIMITER OUT+/OUT50 VCC - 2V RSSI
CIN
FWD
FWD
FWD
FWD
FILTER LOS+/LOSCFILTER VCC REF
MAX3761/MAX3762
INV FWD = FULL-WAVE DETECTOR R1 R2 VTH GNDO
Figure 1. Functional Diagram
_______________Detailed Description
Figure 1 shows the functional diagram for the MAX3761/ MAX3762. The input signal is applied to VIN+ and VIN-. A chain of amplifier stages, each contributing approximately 12.5dB of gain, amplifies the input signal to PECL output voltage swings. A 4mVp-p input signal will cause the output to fully limit.
The high-speed RSSI signal is filtered with one external capacitor connected from FILTER to VCC. The impedance at the FILTER pin is approximately 500. The FILTER capacitor (CFILTER) must be connected to VCC for proper operation.
Input-Offset Correction
The limiting amplifier provides approximately 60dB of gain. An input DC offset of even 1mV reduces the power-detection circuit's accuracy and can cause the output to limit. A low-frequency feedback loop is integrated into the MAX3761/MAX3762 to remove input offset. DC coupling the inputs is not recommended, as this prevents the DC-offset-correction circuitry from functioning properly. Input offset is typically reduced to less than 100V. The capacitance between pins CZP and CZN, in parallel with a 10pF integrated capacitance, determines the offset-correction circuit's time constant. The input impedance between CZP and CZN is approximately 800k. The offset correction circuitry requires an average datainput duty cycle of 50%. If the input data has a different average duty cycle, the output will have increased pulse-width distortion.
Received-Signal-Strength Indicator (RSSI)
Each amplifier stage contains a full-wave logarithmic detector (FWD). The full-wave detector outputs are summed at the FILTER pin and used to generate the received-signal-strength indication (RSSI). The RSSI output voltage is linearly proportional to the input power (in decibels), and is approximated by: VRSSI(V) = 1.13 + 0.457log (VIN ) where VIN is the peak-to-peak input signal in millivolts. The RSSI output is insensitive to fluctuations in temperature and supply voltage. The power detector functions as a broadband power meter that detects the total power of all signals present in the passband of approximately 750MHz. Refer to the Typical Operating Characteristics graphs showing RSSI output versus input power and signal amplitude.
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
Loss-of-Signal Indicator
The MAX3761/MAX3762 includes a loss-of-signal monitor with a programmable assert threshold and a hysteresis comparator. Internally, one comparator input is tied to the RSSI output signal and the other is tied to the threshold-voltage (VTH) pin, which provides a threshold for the LOS indication. An op amp referenced to an internal bandgap voltage (1.18V) is supplied for programming a supply-independent threshold voltage. Only two external resistors are needed to program the LOS assert level. VTH is programmable from 1.18V to 2.4V, providing adequate coverage of the RSSI output's useful range. The op amp runs on very low supply current and provides an accurate, temperature-stable threshold, but can source only 20A of current. For proper operation, resistor R1 (see the Typical Operating Circuit) should have a value 100k. The input bias current at INV is < 50nA. To ensure chatter-free LOS operation, the internal LOS comparator contains approximately 90mV of hysteresis. The RSSI signal output has a slope of 25mV/dB. Therefore, the overall circuit hysteresis is approximately 3.6dB[90mV / (25mV/dB)]. The LOS assert threshold is 45mV below VTH, while the LOS deassert threshold is 45mV above VTH. DISABLE to LOS+ implements a squelch function. When using the squelch function, the output signal is disabled whenever the input signal is too small to be reliably detected (as determined by the voltage at VTH). Use of the disable function is recommended at all times. The data outputs (OUT+ and OUT-) are implemented with emitter followers that have output impedance of approximately 2. The MAX3762's PECL LOS outputs also are implemented with emitter followers that have output impedance of approximately 2. The MAX3761 TTL LOS output buffers are open-collector transistors with 6k internal pull-up resistors.
MAX3761/MAX3762
__________________Design Procedure
Supply Voltage
The MAX3761/MAX3762 can be operated with a single +5V or -5V power supply.
Programming the LOS Assert Level
First determine the receiver system's sensitivity in dBm either by estimating or from prototyping results. Estimate the total gain of the preamplifier and photodiode, then use Figure 3 to select resistor R2, placing the LOS assert 3dB to 4dB below the receiver sensitivity. Alternatively, use the Typical Operating Characteristics to select the VTH value needed for LOS assert, then program VTH with the following relation: VTH = 1.18(1 + R2 / R1) Select R1 100k.
Output Buffers
The DISABLE pin can be used to disable the dataoutput buffer. When DISABLE is high, the differential output signal at OUT+ and OUT- is approximately zero. In the disabled state, the common-mode voltage of each output is approximately VCC - 0.8V. Connecting
R1 = 100k RSSI VOLTAGE VALUE OF R2 (k) 70 60 50 40 30 20 1.2V 3.6dB typical 10 0 -38 VASSERT (min) VDEASSERT (max) -36 -34 -32 -30 -28 -26 -24 INPUT SIGNAL (dBm) GAIN = 2000 GAIN = 4000 GAIN = 6000
25mV/dB VDEASSERT VTH VASSERT 45mV 45mV
-22
INPUT SIGNAL AMPLITUDE
GAIN IS PHOTODIODE RESPONSIVITY x TRANSIMPEDANCE GAIN. EXTINCTION RATIO OF 10 IS ASSUMED.
Figure 2. Loss-of-Signal Definitions
Figure 3. Using TIA Gain and Photodiode Responsivity to Select LOS Programming Resistor
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MAX3761/2-03
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3761/MAX3762
Capacitor Selection
A typical MAX3761/MAX3762 implementation requires four external capacitors. To select the capacitors, first determine the following parameters in the receiver system (see the Applications Information section for recommendations in 622Mbps ATM and Fibre Channel 1063Mbps systems): 1) The duration of the expected longest run of consecutive bits in the data stream. For example, 72 consecutive zeros in a 622Mbps data stream have a duration of 116ns. 2) The maximum allowable data-dependent jitter. 3) The desired power-detector integration time constant [1 / (2INT)]. f 4) The transimpedance amplifier's maximum peak-topeak output voltage. Step 1. Select the Input AC-Coupling Capacitors (CIN). When using a limiting preamplifier with a highpass frequency response, select C IN to provide a lowfrequency cutoff (f C ) one decade lower than the preamplifier low-frequency cutoff. This causes nearly all data-dependent jitter (DDJ) to be generated in the preamplifer circuit. For example, if the preamplifier's lowfrequency cutoff is 150kHz, then select CIN to provide a 15kHz low-frequency cutoff. Select CIN with the following equation: 1 CIN = 2fC 1950 For differential input signals, use a capacitor equal to CIN on both inputs (VIN+ and VIN-). For single-ended input signals, one capacitor should be tied to VIN+ and another should decouple VIN- to ground. When using a preamplifier without a highpass response, select CIN to ensure that data-dependent jitter is acceptable. The following equation provides an estimate for CIN: CIN - tL DDJ BW 1950 ln 1 - 0.5
value of CIN. The following equation estimates LOS time delay when the maximum-amplitude signal is instantaneously removed from the input, and when the FILTER time constant is much faster than the input time constant (CFILTER < 0.4CIN): tLOS ASSERT = 1950CINln(VMAXp-p / VASSERTp-p) where VMAXp-p is the maximum output of the preamplifier, and VASSERTp-p is the input amplitude that causes LOS to assert. The equation describes the input capacitors' discharge time, from maximum input to the LOS threshold into the 1950, single-ended input resistance. Step 2. Select the Offset-Correction Capacitor (CAZ). To maintain stability, it is important to keep a onedecade separation between fC and the low-frequency cutoff associated with the DC-offset-correction circuit (fOC). The input impedance between CZP and CZN is approximately 800k in parallel with 10pF. As a result, the low-frequency cutoff (fOC) associated with the DCoffset-correction loop is computed as follows: fOC = 1 2800k C AZ + 10pF
(
)
where CAZ is an optional external capacitor between CZP and CZN. If CIN is known, then: C AZ CIN - 10pF 41
(
)( )

Step 3. Select the Power-Detect Integration Capacitor (CFILTER). For 622Mbps ATM applications, Maxim recommends a filter frequency of 3MHz, which requires CFILTER = 100pF. The integration frequency can be selected lower to remove low-frequency noise, or to prevent unusual data sequences from asserting LOS. 500fINT) CFILTER = 1 / ( 2 where fINT is the integration frequency.
where: tL = duration of the longest run of consecutive bits with the same value (seconds); DDJ = maximum allowable data-dependent jitter, peak-to-peak (seconds); BW = typical system bandwidth, normally 0.6 to 1.0 times the data rate (hertz). Regardless of which method is used to select CIN, the maximum LOS assert time can be estimated from the
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
__________Applications Information
Converting Average Optical Power to Signal Amplitude
Many of the MAX3761/MAX3762's specifications relate to input-signal amplitude. When working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. The relations given in Table 1 are helpful for converting optical power to input signal when designing with the MAX3761/MAX3762.
MAX3761/MAX3762
OPTICAL POWER P1
PAVE
P0
Table 1. Optical-Power Relations*
PARAMETER Average Power Extinction Ratio Optical Power of a "1" Optical Power of a "0" Signal Amplitude SYMBOL PAVE re P1 P0 RELATION
TIME
Figure 4. Optical-Power Relations
PAVE = (P0 + P1) / 2 re = P1 / P0 P1 = 2PAVE re re + 1
In an optical receiver the dB change at the MAX3761/ MAX3762 will always equal 2x the optical dB change. The MAX3761/MAX3762's typical voltage hysteresis is 3.6dB. This provides an optical hysteresis of 1.8dB.
P0 = 2PAVE / re + 1
(
) (re - 1)
re + 1
Input Sensitivity
The receiver's gain sensitivity defines the smallest signal input that results in fully limited PECL-compatible data outputs. Smaller signals result in nonlimited outputs. The MAX3761/MAX3762's input sensitivity (SGAIN) is 4mVp-p: SGAIN = 4mV Optical gain sensitivity (in dBm) is: S r +1 10log GAIN x e x 1000 re - 1 2G In a receiver with G = 6k, re = 10, and = 0.8A/W, gain sensitivity is 510nW, or -32.9dBm.
PIN
PIN = P1 - P0 = 2PAVE
* Assuming a 50% average input data duty cycle (true for SONET/ATM data).
In an optical receiver, the input voltage to the limiting amplifier can be found by multiplying the relationship in Table 1 with the photodiode responsivity (p) and transimpedance amplifier gain (G).
Optical Hysteresis
Power and hysteresis are often expressed in decibels. By definition, decibels are always 10log (power). At the inputs to the MAX3761/MAX3762 limiting amplifier, the power is VIN2/R. If a receiver's optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the MAX3761/MAX3762 also increases by a factor of two. The optical power change is 10log(2x / x) = 10log(2) = +3dB At the MAX3761/MAX3762, the voltage change is: 10log
622Mbps ATM Component Selection
As an example, a preamplifier with a 150kHz lowfrequency cutoff and a 950mVp-p maximum output has the best performance with the following selections: CIN = 5.6nF, so that fC = 15kHz (one decade below the 150kHz cutoff) C AZ = 150pF, so that f OC < 1.5kHz (one decade below fC) C FILTER = 100pF, so that the integration frequency equals 3MHz. These selections should provide data-dependent jitter less than 110ps p-p when the input consists of PRBS data with no more than 72 consecutive bits.
(2y)2 / R
y2 / R
= 10log(22 ) = 20log(2) = + 6dB
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3761/MAX3762
For LOS assert at -35dBm, select R1 = 100k and R2 = 22k, which programs the LOS assert at input 3mV. With this selection, LOS assert time will typically be less than 85s.
Fibre Channel Component Selection
In Fibre Channel applications, the desired LOS assert time is typically 25s maximum, and data-dependent jitter is reduced by 8B10B coding techniques. The following are recommended in a Fibre Channel system where preamp gain is 2000V/W, LOS assert is set for -24dBm (13mV MAX3761/MAX3762 input), and the maximum input to the MAX3761/MAX3762 is 1Vp-p: CIN = 3.3nF (to provide LOS assert in 25s) CAZ = 82pF (to provide fOC = 1/10 fC for stability) CFILTER = 100pF (for a 3MHz integration constant) R1 = 100k, R2 = 50k (to set LOS assert at -24dBm)
MAX3761
OUT+ 470 50
OUT470 50
DRIVING 50 TO GROUND
PECL Terminations
The standard PECL termination (50 to VCC - 2V) is recommended for best performance and output characteristics. The data outputs operate at high speed, and should always drive transmission lines with 50 to 75 terminations. Balanced termination is recommended for all outputs. Figure 5 shows an alternative method for terminating the data outputs. The technique provides approximately 8mA DC bias current, with a 50 AC load, for the output termination. This technique is useful for viewing the output on an oscilloscope or changing the PECL reference voltage. The MAX3762's PECL LOS outputs are relatively slow and do not need 50 terminations (although they are capable of driving them). To reduce power, the MAX3762's LOS outputs can be terminated with 500. Figure 6 shows a typical operating circuit for the MAX3762.
Figure 5. Alternative PECL Termination
Wire Bonding
For high current density and reliable operation, the MAX3761/MAX3762 use gold metalization. Make connections to the dice with gold wire only, and use ballbonding techniques (wedge bonding is not recommended). Die-pad size is 4 mils square, with a 6 mil pitch. Die thickness is 12 mils (0.3mm).
Layout Techniques
The MAX3761/MAX3762 are high-frequency, highbandwidth circuits. To ensure stability, use good highfrequency layout techniques. Filter voltage supplies, and keep ground connections short. Use multiple vias where possible. Use controlled-impedance transmission lines to connect the MAX3761/MAX3762 data outputs to other circuits.
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
_____________________________________Typical Operating Circuits (continued)
MAX3761/MAX3762
+5V VCC EN 10nF RSSI VCCO 100pF CIN 5.6nF VIN+ CIN 5.6nF VINFILTER 100pF +VCC R1 R2 CFILTER INV VTH CZP CZN DISABLE LOS+ LOSOUTOUT+
CAZ 150pF
500 500 50 50 VCC - 2V VCC - 2V
MAX3762
GNDO GND SUB
VCC - 2V
___________________Chip Topography
RSSI FILTER DISABLE LOS+
EN V CC VIN+ VINGND SUB
LOSV CC VCCO OUT+ OUTGNDO 0.063" (1.60mm)
CZP
CZN
INV
VTH
0.059" (1.49mm)
TRANSISTOR COUNT: 961 SUBSTRATE CONNECTED TO SUB
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Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3761/MAX3762
________________________________________________________Package Information
DIM INCHES MILLIMETERS MAX MIN MIN MAX 0.068 0.061 1.55 1.73 0.004 0.0098 0.127 0.25 0.061 0.055 1.40 1.55 0.012 0.008 0.20 0.31 0.0075 0.0098 0.19 0.25 SEE PIN COUNT VARIATIONS 0.157 0.150 3.81 3.99 0.25 BSC 0.635 BSC 0.244 0.230 5.84 6.20 0.016 0.010 0.25 0.41 0.035 0.016 0.41 0.89 SEE PIN COUNT VARIATIONS SEE PIN COUNT VARIATIONS 8 0 0 8 DIM PINS D S D S D S D S 16 16 20 20 24 24 28 28 INCHES MILLIMETERS MIN MAX MIN MAX 0.189 0.196 4.80 4.98 0.0020 0.0070 0.05 0.18 0.337 0.344 8.56 8.74 0.0500 0.0550 1.27 1.40 0.337 0.344 8.56 8.74 0.0250 0.0300 0.64 0.76 0.386 0.393 9.80 9.98 0.0250 0.0300 0.64 0.76
21-0055A
D A e B
A1
S
A A1 A2 B C D E e H h L N S
E
H h x 45 A2
N E C L
QSOP QUARTER SMALL-OUTLINE PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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Price & Availability of MAX3761

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